Integrated circuit (IC) semiconductor chips are the critical components found in virtually all modern telecommunications, computer, and electronics products. Many of these semiconductor chips are custom-made and tailored to the exact specifications supplied by the designers. However, these dedicated custom chips can be quite expensive to produce. Hence, they are not ideally suited for those instances where only a limited quantity of chips are desired. Furthermore, it can take quite a long time to fabricate these custom chips. In today's competitive environment, time-to-market is of utmost importance. Crucial market share might be irretrievably lost while a company waits for its custom chips to be produced and delivered. And if there is an error somewhere in the initial design or layout, more delays are incurred in fixing the problems.
In response to the shortcomings inherent to custom IC chips, field-programmable gate arrays (FPGAs) were developed. An FPGA is a standard off-the-shelf semiconductor chip that can be individually programmed to perform the desired functions. An FPGA can be reprogrammed an unlimited number of times and can be used in innovative designs where hardware is changed dynamically, or where hardware must be adapted to different user applications. An FPGA is typically comprised of three major configurable elements: configurable logic blocks (CLBs), input/output blocks (IOBs), and interconnect lines. The CLBs provide the functional elements for constructing the desired logic. The IOBs provide the interface between the package pins and internal signal lines. Finally, the interconnect lines provide routing paths to connect the input and output terminals of the CLBs and IOBs onto the appropriate networks. The desired circuit design is established by programming internal static memory cells to control the logic functions and interconnections that are used to produce the desired results.
Typically, there are three main types of interconnect lines, which are distinguished by the relative length of their segments: single-length lines, double-length lines, and long lines. The single-length lines are comprised of a grid of horizontal and vertical metal lines that intersect at a switch matrix between each CLB. The switch matrix, which includes a plurality of programmable transistors, establishes connections between the single-length lines. The double-length lines consist of a grid of metal segments that are twice as long as the single-length lines. Hence, a double-length line runs past two CLBs before entering a switch matrix. Long lines form a grid of metal interconnect segments that run the entire length or width of an array.
FIG. 1 illustrates a prior art FPGA 101 which includes CLBs 102-117, decoders 118-121, IOBs 122-125, and long lines 126-131. Each of the long lines 126-131 has a programmable splitter switch positioned approximately at its center. These splitter switches 132-137 enable the long lines 126-131 to be separated into two independent routing channels, each of which runs half the width or height of the array. For example, splitter switch 134 can be closed so that the segments 138 is electrically connected to segment 139. Hence, a signal originating from CLB 104 can be routed by long line 129 to CLB 116. Alternatively, splitter switch 134 can be in an open position so that the two segments 138 and 139 are separate, thereby allowing segment 138 to conduct signals between CLB 104 and CLB 108 and segment 139 to conduct signals between CLB 112 and CLB 116. However, one shortcoming associated with FPGA 101 is that a long line can only conduct a maximum of two signals at any given time. Hence, a need arises for a different, more flexible approach that allows more signals to be handled by a long line, and yet retains the capability of a long line to conduct a signal the full width or height of the array.
Another disadvantage of FPGA 101 is that the long lines are often used in part of a critical path. As such, it is essential that the signals on the critical path be routed as quickly as possible to increase the overall speed of the chip. In typical FPGAs, the long lines are made of passive metal conductors, wherein the splitter switches simply connect and disconnect the long line segments. Therefore, a further need arises for a mechanism that actively drives the signals on a long line so as to speed up critical path signals. Moreover, it would be preferable if such a mechanism were hi-directionally buffered so that signals could be actively driven in either direction on a long line.
Buffers are advantageously inserted and used in a conductive line when the effect of the buffer is to increase the speed of signal flow. Short lines are typically connected together by pass transistors or transmission gates which are not buffered because the buffer would slow down the signal flow. In a typical FPGA, a number of horizontal and vertical long interconnect lines spanning the array are used to carry signals from one configurable logic block to another configurable logic block. Connections from one long line to another are typically buffered because the buffer increases the speed of signal flow (the performance).